The present invention relates to semiconductor memory devices, and more particularly relates to a dynamic semiconductor memory device formed using a logic process and a semiconductor integrated circuit device in which the dynamic semiconductor memory device is placed with a logic circuit.
Dynamic semiconductor memory devices (DRAMs) which have been used in recent years have increased capacity and a reduced size while driving voltage of the DRAMs has been reduced to be almost 1 V. More specifically, the driving voltage of a DRAM of the 0.18 μm process generation is 1.8 V, that of the 0.15 μm is 1.5 V, and, furthermore, that of the 0.13 μm generation is 1.2 V.
Under such circumstances, in order to ensure an operation margin at a low voltage, various measures have been taken in forming a DRAM circuit. For example, in a DRAM including a transistor and a capacitor (i.e., a DRAM of the 1T1C structure) or a DRAM of an NMOS memory cell type, the threshold voltage (which will be herein referred to as “Vt”) of an access transistor (which will be herein referred to as an “access Tr”) is set to be higher than that of Tr in a regular logic transistor or an peripheral circuit to reduce leakage current, the voltage of a word line is increased to maximize the quantity of electric charge written onto a memory cell, or like measures are taken. In this case, when the potential of a word line is increased, the potential is increased to be higher than a power supply voltage by the threshold voltage of the access Tr or more. Note that in this structure, it is necessary to use a transistor in which a thick gate oxide film is used or to take like measures so that the access Tr resists an increased potential.
These bias structures have been widely used for the purpose of ensuring operation margins for recent DRAMs of the megabit-class or more. Moreover, a structure in which the potential of part of a substrate located in a memory cell region is set to be negative for the purpose of achieving reduction in leakage current in an access Tr, suppression of influence of the substrate bias effect or the like has been widely used.
Furthermore, as for recent system LSIs, the technique of forming a DRAM using a logic process is one of techniques particularly drawing attention. For example, an example of the technique is described in National Publication of Translated Version No. 2002-522871 filed in the name of “On-chip word line voltage generation for DRAM embedded in logic process”. FIG. 16 is a circuit diagram illustrating the configuration of a memory cell of a DRAM in the case where the DRAM is formed using a logic process.
The DRAM of FIG. 16 includes a word line 1001 and a bit line 1002 intersecting with each other and a memory cell provided around the intersection of the word line 1001 and the bit line 1002. The memory cell includes a p-channel MOSFET, i.e., an access transistor (access Tr) 1003 in which the word line 1001 is connected to a gate electrode and which has a terminal connected to the bit line 1002, and another p-channel MOSFET, i.e., a cell capacitor 1004 which is connected to the other terminal of the access Tr 1003 and functions as a capacitor. The cell capacitor 1004 includes a cell plate electrode 1006. The potential of the cell plate 1006 is a first negative increased potential VBB1 (0 V>VBB1). Moreover, the potential of a substrate shared by the access Tr and the cell capacitor 1004 or a well electrode 1005 is a first increased potential VPP1.
In a DRAM formed using the above-described logic process, a cell capacitor and an access Tr are formed of MOS transistors having the same structure as that used for a logic gate. In addition, the following contrivance has been made in a word line, a cell plate, a bias structure of a substrate potential (well potential) for the purpose of achieving both of an increased operation margin of the DRAM (specifically, at a low voltage operation) and charge holding properties.
First, the potential of the word line 1001 in an activated state is set to be a second increased potential Vpp2 which is higher than the power supply potential VDD and an amount of charge written on a memory cell storage node 1007 is maximized to ensure an operation margin. Moreover, the potential of the word line 1001 in a non-activated state is set to be a second negative increased potential VBB2 which is lower than the ground potential VSS, so that a leakage current from the access Tr 1003 is reduced. Furthermore, the substrate potential of the access Tr 1003 is also set to be the first increased potential VPP1 (>VDD), so that leakage current is suppressed. Using these methods, charge retention characteristics of a memory cell can be improved.
Moreover, the potential of the cell plate electrode 1006 is set to be VBB1(<VSS) to keep the cell capacitor 1004 in a state where a channel is formed at all the time. Thus, the cell capacitance of the cell capacitor 1004 is not dependent on a write potential onto the memory cell storage node 1007 from the bit line 1002, but is stably ensured.
As has been described, in the known DRAM formed using a logic process, the potential of a word line is increased in an activated state and is negatively increased in a non-activated state. Moreover, by negatively increasing the cell plate potential and, furthermore, by increasing the substrate potential, desired characteristics of a memory cell are ensured.
If the structure of the above-described DRAM is used, an operation margin is increased and leakage current can be also reduced. However, in order to perform a storing operation in the known DRAM, besides to the power supply potential VDD and the ground potential VSS, four bias voltage sources, i.e., second negative increased potential VBB2 and second increased potential VPP2 for a word line, a bias potential for a cell plate electrode VBB1, and an increased potential VPP1 for a substrate (well) bias, are required. Thus, the same number of circuits for bias or power supply circuits as the number of the bias voltages have to be provided in a chip. Moreover, for a bias of a word line, a driver circuit for controlling two biases, i.e., VPP2 (>VDD) and VBB2 (<VSS) is needed. If this structure is formed, a circuit configuration becomes complex and, moreover, a bias circuit and a driver circuit are needed. Therefore, a disadvantage of largely increasing the chip area of an LSI is caused.